notes - mDDR config/timing

GPIO MUX Regisgter Definition is in In Appendix A

8a0 : bit 9 = 1 DDR2 Input
50c/510 : control signal hystersis, slew rate..
83c/848 : drive strength
4b8 : SDCLK setting (pull up/down, drive strength, slew rate)
4bc/4c0/4c4/4c8 : SDQS(0.1.2.3) setting (hystersis, pull up/down, driver strength, slew rate)
820 : D0-D31 pull up enable
4a4 : RAS (drive strength, slew rate)
4a8 : CAS (drive strength, slew rate)
4ac : SDWE (pull up/down, drive strength, slew rate)
4b0/4b4 : SDCKE(0.1) (pull up/down, drive strength, slew rate)
82c : D24-D31 drive strength
8a4 :D0-D7 drive strength
8ac : D8-D15 drive strength
8b8 : D16-D23 drive strength

SDRAM/DDR Control in DataSheet Chap 30
ref my ddr timeing notes

ESDCTL0/1 :

8

• 31 SDE =1
• 30-28 refresh cycle = 0 (disabled)

3

• 27 reserved = 0
• 26-24 row address width = 011 (14 Row Address)

A

• 23 double the RFC setting = 1
• 22 reserved = 0
• 21-20 Colume Address Width = 10 (10 bit)

2

• 19-18 reserved = 00
• 17-16 Data Width = 10 (32 bit)

0

• 15 self refresh timer = 0
• 14 self refresh timer = 0
• 13 power down timer = 0
• 12 power down timer = 0

000

• 11-0 reserved

ESDMISC

0

• 31 CS0_RDY = 0 (?) page 808
• 30 CS1_RDY = 0
• 29 ODT_IDLE_ON (On Die Terminator) = 0
• 28 SDCLK EXT = 0

0

• 27 termination resistor (DQS3 DQ31-24) terminator select (No termination) = 0
• 26 termination resistor (DQS3 DQ31-24) terminator select (No termination) = 0
• 25 termination resistor (DQS2 DQ23-16) terminator select (No termination) = 0
• 24 termination resistor (DQS2 dQ23-16) terminator select (No termination) = 0

0

• 23 termination resistor (DQS1
• 22
• 21 termination resistor (DQS0
• 20

A (for JEDEC compliant)

• 19 auto precharge AP bit
• 18 -
• 17 -
• 16 -

0

• 15 DIFF_DQS_EN, Differential DQS disabled = 0 (確認 mDDR 只有 CLK 是 differential)
• 14 AUTO_DLL_PAUSE = 0 (this mDDR doesn't need this - list on the cover page)
• 13 ODT_EN = 0 (確認 這個 mDDR 沒有 ODT)
• 12 BI_ON (Bank Interleaving ) = ? (mDDR datasheet 有，但是不確定要不要用)

0

• 11 FRC_MSR (measurement ?) = 0
• 10 MIF3 mechanism = 0
• 9 MIF3 mechanism = 0
• 8 Read Additional Latency (disabled) = 0

0

• 7 Read Additional Latency (disabled) = 0
• 6 DDR2_8_Bank = 0 (這個 mDDR 是 4 bank)
• 5 Latency Hiding Disable for read = ? (要確認 mDDR 需不需要)
• 4 DDR2_EN = 0 (Not DDR2 device)

0

• 3 DDR_EN = 0 (both DDR2_EN & DDR_EN = 0 , will be in mDDR Mode)
• 2 reserved = 0
• 1 RST , software reset = 0
• 0 reserved = 0

ESDCFG0/1

Working on 200MHz, 1 clk = 5nS

• 31-28 tRFC (120nS =24 clk) = 1110
• 27-24 tXSR (120nS = 24clk) = 0000
• 23-21 tXP (no data, set to max) = 111
• 20 tWTR (no data, set to max) = 1
• 19-18 tRP (18nS = 4clk) = 10
• 17-16 tMRD (2tCK =12nSx2 =24nS = 5 CLK, use 4) = 11
• 15-12 tRAS (42nS = 9clk) = 1000
• 11-10 tRRD (12ns = 3clk) = 10
• 9-8 reserved = 00
• 7 tWR (12nS = 3clk) = 1
• 6-4 tRCD (18ns = 4clk) = 11
• 3-0 tRC (60nS = 12clk) = 1010

Mode Register Set (MRS)

對應的是 SDRAM Special Command Register (p30-34)
ref my SDRAM Mode Register Notes

from mDDR DataSheet.

Mode Register Set 的內容：

• A6-A4 : CAS Latency
• A3 - Brust Type
• A2-A0 : Burst Length

controller 的 Load Mode Register :

• bit 30-16 : 對應 A14-A0
• bit 5-3 : CMD - 要作的事 - 011 - Load Mode Register

DataSheet 的 example 是：

• 04008008 -- precharge
• 00008010 -- refresh
• 00338018 -- Load Mode Register -- CAS = 3, BL=2 (Burst Length=8), Burst Type = sequential
• 0020801A -- Extend Mode Register - half strength, Full Refresh